DEVICE CROSS-SECTION · n-FeFET
● IDLEGATE CONTROL
V_DS = 0.1 VKeys: ←→ nudge V_G · P program · E erase · R read · S sweep
GATE WAVEFORM V_G(t)
Ferroelectric hysteresis · P–V
Transfer curve · log I_D–V_G
Drag V_G slowly from −3 V to +3 V. Each domain flips at its own coercive voltage — the P–V scope traces the hysteresis loop as you go.
Press SWEEP. The I_D–V_G scope draws two split curves. The gap between them, ΔV_TH, is the memory window — set by P_r and t_FE.
PROGRAM, then READ. At V_G = 0 V the channel conducts → stored “1”. Now ERASE and READ again → “0”. The read is non-destructive.
The memory cycle, in four acts
The ferroelectric layer (here Hf₀.₅Zr₀.₅O₂) sits inside the gate stack. Its dipoles can be switched by the gate field and — crucially — they stay switched when power is removed. That remanent polarization shifts the transistor's threshold voltage, and that shift is the bit.
Program — flip the dipoles down
A positive gate pulse beyond the coercive voltage (+V_P > V_C) snaps the dipoles toward the channel. Their bound positive charge at the interface attracts electrons, so the threshold voltage drops by ΔV_TH = P_r·t_FE / (ε₀·ε_FE). Switching is intrinsic to the crystal lattice — nanoseconds, no charge pumping.
Hold — a bistable energy landscape
Remove all power and the bit stays put. The ferroelectric phase has a double-well free energy: two stable polarization orientations separated by a barrier E_b. Thermal energy at room temperature can't kick a domain over the barrier, so the state is non-volatile for years — a bistable switch built into the material itself.
Read — probe with a small voltage
Apply a modest V_read between the two threshold voltages. The programmed cell (low V_TH) conducts — microamps, logic 1. The erased cell (high V_TH) is off — picoamps, logic 0. Because V_read stays far below V_C, the dipoles don't move: unlike DRAM, the read doesn't destroy the data.
Erase — flip back with a negative pulse
A negative pulse (−V_P < −V_C) reorients the dipoles toward the gate. The bound charge at the channel interface turns negative, the surface depletes of electrons, and V_TH rises again. The cell returns to “0” — and the whole loop can repeat 10⁵–10⁹ times before fatigue sets in.
Why hafnium oxide changed everything
Ferroelectrics used to mean exotic ceramics — lead-based PZT or layered SBT — that a silicon fab would never touch. Then in 2011, ferroelectricity was discovered in Si-doped HfO₂: the very oxide already sitting in every logic fab as the high-k gate dielectric.
Hf₁₋ₓZrₓO₂ (HZO), annealed under confinement, locks into a non-centrosymmetric orthorhombic phase (Pca2₁) whose unit cell carries a switchable dipole. Remanent polarization reaches 10–40 µC/cm² at under 10 nm thickness — thin enough to scale with logic, robust enough to remember.
That is what makes the FeFET practical: a non-volatile memory built entirely from materials and thermal budgets the CMOS line already owns, added in a few extra steps to a plain transistor.
FeFET vs. the field
Where one-transistor ferroelectric memory sits among the established technologies.
| FeFET | Floating-gate Flash | DRAM | |
|---|---|---|---|
| Bit stored as | Dipole orientation (polarization) | Trapped charge on a floating gate | Charge on a capacitor |
| Cell | 1 transistor | 1 transistor (+ selector) | 1 transistor + 1 capacitor |
| Write mechanism | Lattice polarization switching | Fowler–Nordheim tunneling | Charge sharing |
| Write speed | ~ns | µs – ms | ~ns |
| Write voltage | ~2–4 V | 10–20 V (on-chip pump) | ~1 V |
| Endurance | 10⁵ – 10⁹ | 10³ – 10⁵ | > 10¹⁵ |
| Non-volatile | yes | yes | no — refresh every ms |
| Scaling bottleneck | FE film quality < 10 nm | tunnel oxide reliability | capacitor aspect ratio |